1. Field of the Invention
The present invention relates generally to computer network applications, and more particularly to computer network applications which facilitate the design of integrated circuits.
2. Related Art
In today""s technological climate, there is a continuing advancement in computing technology and processing power, as well as the increased availability of computing facilities and platforms. Despite such computing technology progress, however, the process of designing integrated circuits has remained stagnant. That is, today""s engineers still undergo a mostly manual process when designing and testing integrated circuits (or xe2x80x9cchipsxe2x80x9d) for use in electronic products.
In general, the chip design process can be viewed and explained as a series of six sequential phases: (1) system architecture exploration; (2) software development; (3) design; (4) verification; (5) synthesis, layout and static timing analysis (STA); and (6) auto test pattern generation (ATPG).
First, in the system architecture exploration phase, a chip designer explores different system architectures. Depending on the requirements of the system (i.e., the product) for which the chip is being designed, the chip designer may need to analyze any or all of the following factors: frequency/performance; bus bandwidth and latency; interrupt latency; memory latency and bandwidth; cache size; and software compatibility. Today, much of this is done manually, although using a cycle-accurate simulator sometimes helps. With the advent of multi-million gate SOC (xe2x80x9csystem on chipxe2x80x9d or application specific integrated circuit (ASIC)) designs, the above analyses may be required for multiple cores on a chip.
Second, in the software development phase, the designer makes hardware/firmware/driver determinations for the system. Many different methodologies are now employed. Often, the chip design engineer needs actual hardware to do software development. If this is the case, they must decide whether to purchase standard boards or wait until their chip is actually manufactured before starting software design. In many cases, design engineers desire to start software development simultaneously with hardware development. Conventional tools exist that model hardware behavior in order to enable early software design. Many of these are part of an integrated software development environment (IDE) that offers project management, compilation control and debug functionality. These tools, however, are stand-alone and not integrated into the other five phases of chip design.
Third, in the design phase, the actual register transfer level (RTL) design is typically done as a manual process using pencil and paper, or some computer screen editor (e.g., Emacs). In some cases, a graphical interface may be used to design state machines using state transition diagrams. As will be appreciated by one skilled in the relevant art(s), a state transition diagram consist of circles to represent states and directed line segments to represent transitions between the states, wherein one or more actions (outputs) may be associated with each transition.
Fourth, in the verification phase, design engineers typically utilize simulators to xe2x80x9cloadxe2x80x9d the developed software onto the designed hardware (i.e., the chip). The verification phase, in essence, involves the design engineer determining if the chip functions as called for in the design specification. Such functional verification is computer intensive. Generally speaking, the chip designer submits their design and then executes some type of electronic design automation (EDA) tool (e.g., simulators, formal verifiers or code linters). After the EDA tool is executed, the engineer analyzes the results. These results are in the form of text log files and result files. Then, graphical waveform viewing is also often done after simulations. One shortcoming of this process is that the design engineer must manually submit designs as well as manually verify the rest of the chip design, then manually build a simulation engine. More experienced engineers find this process relatively simple, yet error prone. More novice design engineers, however, find a need to keep careful notes given that the process is fairly detailed and manual.
Fifth, in the synthesis, layout and STA (collectively referred to as the xe2x80x9cback-endxe2x80x9d) phase, the following user inputs are required: the design database (i.e., the RTL module files); synthesis constraints and compile options; and a floor plan (typically the most important user input to layout and is generated using graphical EDA floor planners). The synthesis is the translation of the RTL to actual logic gate implementations. The layout refers to the actual physical placement of gates onto the silicon wafer. STA is the timing verification of the chip (i.e., xe2x80x9chow fast does it run?xe2x80x9d). For most projects, synthesis, layout and STA are computationally intensive tasks with little user interaction. Initially, default synthesis constraints can be used. After that, constraint optimization is mostly done manually, although it can be automated. Most typically, default compile options can be used, although the design engineer may sometimes make manual tweaks. Today, synthesis, layout and STA are typically done by scripts specifically created for each design project.
Sixth, in the ATPG phase, a test sequence is generated. This test sequence is designed in order to test the chip once it has been fabricated (e.g., testing for xe2x80x9cstuck-at zeroxe2x80x9d or xe2x80x9cstuck-at onexe2x80x9d faults in a CMOS chip). The ATPG phase is another design step that is computationally intensive. As done today, it requires the final net list as input with some small user input file. After the test sequence is executed, an engineer analyzes the output log files to see if any improvements can be made in the design.
The final output of the design process is typically a magnetic tape (xe2x80x9ctape-outxe2x80x9d) in the GDSII binary format (developed by Cadence Design Systems, Inc. of San Jose, Calif.), which can then be sent by the design engineer to a foundry for actual fabrication of the chip.
The design flow for an integrated circuit is described in more detail in Michael J. S. Smith, xe2x80x9cApplication Specific Integrated Circuits,xe2x80x9d Addison-Wesley, ISBN 0-201-50022-1 (USA 1997), which is incorporated herein by reference in its entirety.
In sum, the six-phase chip design process explained above is complex and time-consuming. While automated tools exist for certain stages of design (e.g., the Design Compiler(trademark) tool, available from Synopsys, Inc. of Mountain View, Calif. for synthesis and the FastScan(trademark) tool, available from Mentor Graphics Corp. of Wilsonville, Oreg. for ATPG), no single integrated tool is currently available to aide engineers at every stage of product design (i.e., from conception to tape-out).
Given the foregoing, what is needed is a system, method and computer program product for a total integrated circuit design tool.
The present invention, which meets the above-identified need, is a system, method and computer program product for total Web-based integrated circuit design. The present invention allows design engineers to utilize a well-understood graphical interface (i.e., a Web browser) to access a wealth of data and services. The present invention allows designers to evaluate and choose competing standard architectures, and to more efficiently design cores and systems-on-a-chip (SOCs). In essence, the present invention is a xe2x80x9cvirtual labxe2x80x9d which allows and aides design engineers at every stage of product design. This includes, without limitation, architecture choice, implementation options, software development, and hardware design.
The system of the present invention includes an application database that stores information about users of the system and reference designs for integrated circuits. The system also includes a plurality of servers, each connected to the application database, that possess the code logic necessary to provide the virtual lab functionality described herein while accessing the application database. A gateway (i.e., a Web server) is also included which services connections (e.g., Web connections) from a plurality of geographically remote user machines over at least a portion of the Internet. The system also includes means for allowing the plurality of user machines to perform all phases of integrated circuit design by communicating with one of the plurality of servers via the gateway and a graphical user interface.
The method and computer program product of the present invention involve receiving from the user a selection indicative of an application for which the user is designing an integrated circuit (IC). Next, the application database is accessed in order to retrieve reference designs for the selected application.
Then, the user selects, via the graphical user interface (which is provided to the user over at least a portion of the Internet), one of the reference designs for the application. Once a reference design is selected, the user is provided, via the graphical user interface, a system simulation tool, which allows the user to select, simulate and prototype the hardware, software and middleware of the IC being designed.
The method and computer program product also provide the user with a chip design flow tool. The tool allows the user to perform register transfer level design, verification, synthesis, layout and static timing analysis of the IC being designed. Next, the user is provided with one or more compiler and debugger tools in order to facilitate the software development of the IC being designed.
One advantage of the present invention is that a company of design engineers can avoid the purchase of expensive tools for each of the six phases of chip design, some of which are going to be used infrequently. Further, the use of the present invention allows smaller companies (e.g., xe2x80x9cstart-upxe2x80x9d companies) to avoid the purchase of several tools and computing facilities, and having to establish design methodologiesxe2x80x94all of which smaller, newer companies have difficulty doing due to limited capital and inexperience.
Another advantage of the present invention is that can be utilized for xe2x80x9cplatform-basedxe2x80x9d SOC design where a design engineer is presented with several reference design choices that may be, for example, further integrated or modified, as well as xe2x80x9cblock-basedxe2x80x9d SOC design where the design engineer is presented with a list of several design components that may be used to construct a system from scratch (rather than reference designs).
Another advantage of the present invention, as to the system architecture exploration phase, is that a designer can use the Web to xe2x80x9cdrag and dropxe2x80x9d several cores into a design, upload software or a benchmark, and then simulate the system assuming some interconnection scheme. In essence, the present invention allows a chip designer to xe2x80x9ctry before they buy.xe2x80x9d
Another advantage of the present invention, as to the software development phase, is that by making the functionality described herein available over the Web, design engineers save time and energy by not having to install and maintain the software or computer servers used for simulation. That is, an application service provider (ASP) offering the tool of the present invention can make a library of optimized functions available xe2x80x9con-linexe2x80x9d thereby giving software developers a xe2x80x9cjump startxe2x80x9d in industry standard areas like Fast Fourier Transform (FFT), floating point emulation, etc.
Another advantage of the present invention, as to the verification phase, is that the Web can improve these tasks by acting as a xe2x80x9cfront-endxe2x80x9d to a set of common scripts that better manage the entire verification phase process. This can significantly simplify the methods by which engineers design and verify RTL. This would also give novice design engineers a faster learning curve and provide expert design engineers with less opportunities for making oversights. The Web scripts can work closely with a database of circuit verification scripts (CVS) to enable: submission and check-in of designs, release of designs for internal use (i.e., xe2x80x9cSILVER taggingxe2x80x9d), graduation of designs after regressions (i.e., xe2x80x9cGOLD taggingxe2x80x9d), check-out of all current modules for simulation, building of custom simulation engines, access to pre-built simulation engines (SILVER and GOLD), submission of standard regressions to a compute farm, submission of single tests to compute farm or local machine, access to simulation/regression results, including waveforms, and submission of new functional tests to the database.
Another advantage of the present invention, as to the synthesis, layout and STA phase, is that the Web can improve the computationally-intensive tasks in the same way it can improve functional verification. That is, it can automate and standardize these steps and give access to shared computer resources. Because the flow is being automated and simplified, this also gives the ASP the opportunity to offer multiple EDA tool options for synthesis and layout. By offering different flows, design engineers can choose the one that best fits their design flow.
Yet another advantage of the present invention, as to the ATPG phase, is that the Web provides an advantage over conventional techniques by automating and standardizing the ATPG process and provides remote access to computer servers.
Further features and advantages of the invention as well as the structure and operation of various embodiments of the present invention are described in detail below with reference to the accompanying drawings.